- Lattice expands its ECP5™ line of low power, small form factor FPGAs
- First to support 5G SERDES and up to 85K LUTs in a small 10 x 10 mm package
- Cost optimized programmable IO bridging functionality in a 12K LUT device
Portland, OR – February, 2016 – Lattice Semiconductor Corporation (NASDAQ: LSCC), the leading provider of customizable smart connectivity solutions, today announced an expansion of the company’s ECP5™ family of low power, small form factor connectivity and acceleration FPGAs. These new additions are pin compatible with ECP5 FPGAs and enable OEMs to seamlessly update their designs to meet evolving interface requirements in the industrial, communications and consumer markets.
ECP5-5G
Lattice’s ECP5-5G family is the only FPGA product line supporting 5G SERDES and up to 85K LUTs in a small 10×10 mm package. The ECP5-5G devices support multiple 5G protocols including PCI Express Gen 2.0, CPRI, and JESD204B. This product family enables seamless connectivity to ASICs and ASSPs in a wide array of applications including cameras, displays, gaming platforms, small cells and low-end routers. Numerous resources including software, device samples, soft IP and hardware boards are available upon request.
ECP5 12K
The ECP5 12K device offers programmable IO support for popular interface bridging functions including, LVDS, MIPI and LPDDR3. The device provides a cost optimized mix of logic, memory and DSP resources for additional pre and post processing in a variety of applications such as LED controllers, machine vision, motor control and more. Software and device samples are available upon request.
“Our ECP5 FPGA family has proven to be the ideal solution to address the flexible connectivity needs in applications where lower power, smaller form factor and lower cost are critical requirements,” said Deepak Boppana, director of product marketing at Lattice Semiconductor. “The new ECP5-5G and ECP5 12K devices will enable our customers to continue taking advantage of these differentiated features, while accelerating time-to-market of their next-generation designs.”
