Systems today are often comprised of one or more switching , converters, which are used to create an intermediate voltages. Regulators are then used to create additional voltages required by the system. State of the art logic circuits often require 2.5V, 1.8, 1.5 and even sub 1V. At these lower voltages excessive EMI and Noise caused by poor stability are a major concern. For instance, regulation for a 1.5V output requires a tolerance of less than 75mV. This must account for DC regulation, IR drop, conducted susceptibility and load step excursions. So its no wonder we need to assess performance using a combination of test, modeling, and analysis. One issue newer regulators have in common is that the impact of the interconnecting impedance is as important as the output capacitance. So as device sizes shrink, less and less is accessible making testing more difficult.
While this step load response isn’t oscillating, the ringing results in EMI issues that can extend to very high frequencies. As an assessment methodology, WCCA guidelines are focused on Bode Plot Gain & Phase Margin. The Aerospace TOR on WCCA and most Corporate Guidelines state that “All” Control Loops”, including items like high bandwidth opamps, should be assessed for EOL stability. This is an analysis that is not always performed for a variety of reasons. Current guidelines call for 30 degrees PM and 10dB of GM. In the past guidelines used often used 45 degrees and 12dB. So these 2 criteria are about whether we want 3dB of peaking or 6dB of peaking. However, the real measure of performance is what poor stability does to the error budget of the functions poor stability impacts upstream, and overall system performance. This can be very hard to quantify in top‐level testing. The uncertainty forces individual control loop stabilities to be evaluated. In any case, we don t’ always treat stability stability with the importance the importance it deserves deserves and the impedance impedance resonances that occur, and change with age, can create noise paths throughout our system diminishing performance.
So why is test alone not sufficient. Or analysis without hardware correlation for that matter. The answer is that analysis and test each fill in different pieces of the puzzle. Its not always clear what the test setups were that generated the data sheet data. In system test confirms the true performance. Generally there is no documentation on how to tolerance vendor supplied models. But if you make your own models you can setup the model so that it can be toleranced toleranced. There isn t’ always a one to one correspondence correspondence between between the SPICE model parameters and the datasheet characteristics so you need to know how to get the model to give you the electrical performance you want. Getting in under the hood or developing your own models is the only way to understand how to apply tolerances.
VTFM testing is designed to achieve adequate variation of circuit parameters through a choice of voltage, temperature, and frequency margin combinations to achieve an realistic check of the design margin. Basically it uses temperature to emulate EOL tolerances. NASA has determined that this is a viable alternative to WCCA. Why/When is this not the case? What does it miss? When Initial tolerance are large or not impacted When aging or radiation is significant Part stresses or degradation are not seen (Another NASA lesson learned) ‐ From Flight experience Bounded design environments are exceeded Worst case environment doesn’t always occur at the bounds
Inherently g g VTF margin testing doesn’t q y uantify risk/ margin
So how do we assess regulators that do not have their control loops exposed or that have multiple loops? With Non‐Invasive Stability Measurement (‘NISM’). A technique that converts output impedance to stability margin. With NISM software, embedded in our VNA, we record the stability “modulus” margin ‐ minimum distance from the critical point (1, 0) to the open loop transfer function. This is an extension of GM/PM to a more general assessment. There are many papers on this topic including the ESA document mentioned.
You can find more information here https://www.picotest.com/non‐invasive‐stability‐ measurement.html
Practically sp g, eaking, impedance is measured with a suitable probe in a 1 or 2 port configuration. https://www.picotest.com/products_PDN_Probe.html As the name implies the probe and the impedance assessment can be made in‐system, precisely where and h h ow t e measurement sh ld ou b d e ma e. And its non‐invasive. Unlike hooking up an electronic load which can be very capacitive, the act of making the output impedance measurement with a 50 ohm probe such as the one shown, doesn t’ impact the result at all. We have many more examples but suffice it to say NISM is more accurate than a Bode plot and not subject to its failings (multiple crossings, not closest distance to the 1.0 unstable point).
Simulation can be an alternative to test. But only if the models are validated. And that means correlated to actual (valid) test data in a known test setup. Vendor models generally don’t come with documentation. You don’t get to see the schematic topology of the subcircuit unless you draw it out. So while we might not have the full circuitry to test at the time we need the model, model correlation via test is essential to having confidence in your models. That usually means building prototypes or breadboards of the appropriate circuit sections. Here is a simulation of a vendor supplied model and the AEi Systems model. The vendor’s model isn’t even in the ballpark. Its critical to check the output impedance of power ICs. If the output impedance is not right over the ENTIRE range of load current and voltage, there isn’t much the model will be good for. The stability, reverse transfer, step load, and startup responses will all be incorrect.
Taking this a little further, we find that many g re ulators have a very nonlinear performance over the operating ranges and are heavily dependent on the source and load impedance, here represented as capacitance, ESL, and ESR. Most regulators have a tunnel of stability surrounded by ESR and l d oa current ranges. In this t l unne the regul t a or will be st bl a e (PM > 30 deg/GM > 10dB at EOL) Most have stability issues at low current and low ESR and/or high ESR. In this case, at high ESR and higher capacitance the performance performance is reasonable. reasonable. At low ESR the phase margin phase margin is poor due to the phase dip and the gain curve is rising as the phase is dropping (GM issue). So why is the linear regulator’s behavior so nonlinear?
It becomes evident as delve a bit deeper into the model and control loop response revealed via test data and simulation of the transistor level model. These types of gain and phase variation (moving poles/zeros) are very difficult difficult to model and often require require one of two approaches. two approaches. Either we have to use the transistor level model or we have to make multiple models over specific and limited operating conditions (in order to bound the nonlinearities, for example, a low current model that only works at one Vin/Vout combination).
Well lets take a look at the transfer function. This is what was required to model the loop performance at one operating condition. 3 pole‐zero pairs, 2 poles, and a RHP zero! The vast majority of macro models (unless they were mad b e y AEi Systems) h are not this accurate. In fact, most are barely second order. In addition, if your control system is higher than 2nd order, you can have good phase margin that doesn’t necessarily mean you have good stability stability. Bode plots can be misleading. When Bode Plots Fail Us (https://powerelectronics.com/power_systems/circuit_anal ysis/when‐bode‐plots‐fail‐us‐0430/) Added inductance inductance is like is like adding a pole, so you have to account for board layout parasitics.
Accurate Accurate modeling modeling is possible possible and when you have an accurate accurate model then it becomes relatively straightforward to optimize the design. To g g et it right some models need to be built with portions of the actual transistor level model in combination with macro model building blocks.
https://www.aeng.com/pdf/V2h5IFJlZ3VsYXRvcnMgTmVlZCBNb2RlbGluZywgVGVzdGluZywgYW5kIEFuYWx5c2lz.pdf