SEPIC-Fed Buck Topology Increases Performance in Non-Isolated Dc-Dc Converters

Fariborz Musavi, CUI

A point-of-load (POL) converter is a step-down DC-DC converter designed to supply constant voltage to a load, (almost) independently of load currents. It has become a popular solution for a wide variety of applications: from networking and telecommunications to data-communications and computing applications, as well as space technologies.

The use of POL converters is rising rapidly for powering FPGAs, ASICs and other devices with a high-performance processing core. Furthermore with the dynamic power consumed by a processor being proportional to processor frequency and to the square of the processor voltage, the trend is towards lower core voltages that reduce power losses and consequently allow faster processing speed.

And it is obvious that the current capability for these converters will increase even if the power capability stays the same.

This has several implications for the power supply circuitry, including the need to route low voltages at high currents around a printed circuit board. This leads to relatively large voltage drops, higher power consumption, and large PCB tracks, which can easily result in poor output regulation.

By placing the point-of-load (POL) converter near to the load, it is possible to eliminate the long wiring between power supply and load found in conventional power supply systems. This enables a precise voltage supply while also meeting the low-voltage and large-current requirements. Additionally, as the power converters are located in physical proximity to the load circuitry, DC distribution losses are minimized and distribution inductance is reduced, enhancing dynamic response performance.

In summary, these systems demand high levels of current at multiple low-supply voltages, and have tight regulation requirements, with large and fast dynamic currents.

Limitations of Existing POL Topologies

The most common topology used in POL applications is the synchronous buck converter. This replaces a diode with a low-side MOSFET, helping to significantly reduce losses and thereby optimize the overall conversion efficiency compared with a buck converter. Figure 1 illustrates schematic of a synchronous buck converter.

Figure 1: Schematic of a Synchronous Buck Converter.

However, all of this demands a more complicated MOSFET drive circuitry to control both the switches. In addition, care has to be taken to ensure both MOSFETs are not turned on at the same time, which would create a direct short from V_in to ground and cause a catastrophic failure. This short circuit is also called cross-conduction or shoot-through.

While using a MOSFET in place of the catch diode reduces the conduction loss, it also allows bidirectional flow of the inductor current. Thus, the synchronous buck converter maintains operation in its continuous conduction mode (CCM), versus the discontinuous conduction mode (DCM) for a conventional buck converter at light load. So while a synchronous buck converter may yield high efficiencies at high output current, it’s anything but efficient for low output power.

This means improving overall efficiency at both light loads and at high output current, a priority in next generation networking equipment, remains a challenge.

Another limitation of existing topologies can be highlighted by the requirement to supply a highly dynamic current with a tightly regulated voltage. This is a significant problem if using a buck converter as significant output voltage variations will occur during large load transients..

The inductor current’s inability to vary at the speed of the load current causes the output capacitor to provide the necessary current to supply the load during load transients. This, in turn, will cause the output voltage to vary from its designed nominal voltage due to the capacitor discharging. Conversely, a fast “step-down” load transient would result in a voltage overshoot caused by capacitor charging.

Additionally, the controller cannot immediately react to turn on the control switch following the load current step due to its constant-frequency synchronous operation. The controller must, therefore, wait until the succeeding clock pulse before the control switch is turned on again. And, the finite bandwidth of the linear compensator – designed to be a fraction of the switching frequency for the purpose of system stability – prevents the control voltage from increasing at a sufficient rate. These two factors combined cause the capacitor discharge integral to be much larger than the ideal case.

Since the bandwidth of the compensator is designed based on the switching frequency, an obvious solution to improve the above drawbacks would be to simply increase the switching frequency of the converter. However, as already stated, the frequency-dependant losses of a buck converter (MOSFET gate loss, switching loss, inductor core loss), would lead to significant efficiency decreases for the converter.

Physical limitations of semiconductor devices and their current capabilities also play an important role in physical limitations of POLs. In order to design a higher current POL converter, designers either put several MOSFETs in parallel or they adapt multi-phase converter approach. Either way, the size and component cost would increase significantly.

Enter the SEPIC-Fed Buck Topology

CUI has developed a new topology to counter this problem. The proprietary Solus® Power Topology combines a single-ended primary-inductor converter (SEPIC) with a buck converter to form a SEPIC-fed buck. This patented topology addresses several limitations in the existing POL converter solutions, particularly efficiency and transient response. Figure 2 illustrates schematic of a SEPIC-fed buck converter.

Figure 2: Schematic of a SEPIC-Fed Buck Converter.

The ability to reduce power losses is an important aspect of this topology. Increased efficiency is accomplished by reducing both the conduction and switching losses at several critical points within the converter circuit.

At increased switching frequencies, these improvements become even more compelling. The higher the switching frequency could be produced, the higher the power density and the higher bandwidth of the linear compensator, consequently the more cost effective and the better transient response. If we assume that identical switching devices are used in a buck and Solus design, the new topology has the potential to reduce the switching losses by over 90%.

Figure 3 illustrates the converter efficiency versus output current at 12V input and 1V output in a 60 A non-isolated POL design. As it can be noted, the converter’s efficiency peaks at 30A at 91.28%.

Figure 3: 60A SEPIC-fed buck converter efficiency versus output current at 12V input and 1V output.

Figure 4 illustrates the transient response at 12V input and 1V output, to a 30A step change to the load (from 15A to 45A) with 10A/µs slew rate. It is noted that the peak-to-peak voltage change is 32 mV, and the bulk capacitors used in the board are 10×470 uF PosCAPs with no additional ceramic capacitors.

Figure 4: Transient response at 12V input and 1V output, to a 30A step change to the load with 10A/us slew rate.

Ch1 (Blue): Vout, 10mV/div. and Ch2 (Green): Iout, 10A/div.

This allows the Solus converter to operate at a higher switching frequency without sacrificing very much efficiency, permitting benchmark power density at very reasonable levels of efficiency. Furthermore, since the topology has a very flat efficiency curve and can operate very efficiently over a wide voltage range, designers can substantially reduce the amount of the bulk hold-up capacitance as well, reducing the total cost of the power supply.

Input current to the SEPIC-fed buck converter is almost straight dc with only slight ripple, so the input capacitors value could be reduced up to 95%. This input characteristic also reduces EMI caused by input current ripple. This is due to presence of an inductor at the converter input side, which also helps to reduce any chance of failure in case of any shoot-through.

The Solus Power Topology includes one magnetic component, one control switch and two commutation switches that are optimally controlled by pulse-width modulation (PWM). The magnetic component consists of four inductively-coupled inductors wound on the same core. This translates to a level simplicity on par with a traditional buck converter.

Summary

Modern systems are demanding higher levels of current at multiple low-supply voltages, and have tight regulation requirements, with large and fast dynamic currents– indeed, 100A + are not unheard of – and existing topologies are consequentially reaching the limits of their capabilities.

High performance POL power conversion now demands high power density, high efficiency for greener systems, fast transient response and low EMI.

The SEPIC fed buck is the first topology to incorporate the characteristics needed to address these new requirements.

Be sure to visit our booth (1233) at the Applied Power Electronics Conference (APEC) in Fort Worth, TX from March 16-20 to learn more about our solutions to the power challenges of next-generation networking applications, including the latest high density modules based on CUI’s Solus Power Topology.